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Silicon Labs /BGM220SC12WGA /SYNTH_S /DIVCTRL

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Interpret as DIVCTRL

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https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/SYNTH_S/DIVCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LODIVFREQCTRL

Description

No Description

Fields

LODIVFREQCTRL

Frequency division

1 (LODIV1): Divide LO frequency by 1.

2 (LODIV2): Divide LO frequency by 2.

3 (LODIV3): Divide LO frequency by 3.

4 (LODIV4): Divide LO frequency by 4.

5 (LODIV5): Divide LO frequency by 5.

7 (LODIV7): Divide LO frequency by 7.

19 (LODIV6): Divide LO frequency by 6.

20 (LODIV8): Divide LO frequency by 8.

21 (LODIV10): Divide LO frequency by 10.

23 (LODIV14): Divide LO frequency by 14.

27 (LODIV9): Divide LO frequency by 9.

28 (LODIV12): Divide LO frequency by 12.

29 (LODIV15): Divide LO frequency by 15.

36 (LODIV16): Divide LO frequency by 16.

37 (LODIV20): Divide LO frequency by 20.

155 (LODIV18): Divide LO frequency by 18.

156 (LODIV24): Divide LO frequency by 24.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data